research
∙
01/02/2023
Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays
Domain-specific accelerators are used in various computing systems rangi...
share
research
∙
12/06/2022
Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications
Many state-of-the-art deep learning models for computer vision tasks are...
research
∙
11/30/2022
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
The architecture of a coarse-grained reconfigurable array (CGRA) interco...
research
∙
11/23/2022
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
While coarse-grained reconfigurable arrays (CGRAs) have emerged as promi...
research
∙
08/31/2022
The Sparse Abstract Machine
We propose the Sparse Abstract Machine (SAM), an intermediate representa...
research
∙
03/11/2022
Bringing Source-Level Debugging Frameworks to Hardware Generators
High-level hardware generators have significantly increased the producti...
research
∙
11/29/2021
Enabling Reusable Physical Design Flows with Modular Flow Generators
Achieving high code reuse in physical design flows is challenging but in...
research
∙
08/12/2021
Automating System Configuration
The increasing complexity of modern configurable systems makes it critic...
research
∙
05/26/2021
Compiling Halide Programs to Push-Memory Accelerators
Image processing and machine learning applications benefit tremendously ...
research
∙
04/29/2021
Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis
The architecture of a coarse-grained reconfigurable array (CGRA) process...
research
∙
09/18/2020
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator
Using digital standard cells and digital place-and-route (PnR) tools, we...
research
∙
06/20/2020
fault: A Python Embedded Domain-Specific Language For Metaprogramming Portable Hardware Verification Components
While hardware generators have drastically improved design productivity,...
research
∙
02/06/2020
Fast FPGA emulation of analog dynamics in digitally-driven systems
In this paper, we propose an architecture for FPGA emulation of mixed-si...
research
∙
02/01/2019
Dataset Culling: Towards Efficient Training Of Distillation-Based Domain Specific Models
Real-time CNN based object detection models for applications like survei...
research
∙
11/06/2018
Training Domain Specific Models for Energy-Efficient Object Detection
We propose an end-to-end framework for training domain specific models (...
research
∙
09/10/2018
DNN Dataflow Choice Is Overrated
Many DNN accelerators have been proposed and built using different micro...
research
∙
06/24/2016
FPMax: a 106GFLOPS/W at 217GFLOPS/mm2 Single-Precision FPU, and a 43.7GFLOPS/W at 74.6GFLOPS/mm2 Double-Precision FPU, in 28nm UTBB FDSOI
FPMax implements four FPUs optimized for latency or throughput workloads...
research
∙
06/14/2016
A Systematic Approach to Blocking Convolutional Neural Networks
Convolutional Neural Networks (CNNs) are the state of the art solution f...
research
∙
04/08/2009