A WCET-aware cache colouring technique for reducing interference in real-time systems
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The predictability of a system is the condition to give saferbound on worst case execution timeof real-time tasks which are running on it. Commercial off-the-shelf(COTS) processors are in-creasingly used in embedded systems and contain shared cache memory. This component hasa hard predictable behaviour because its state depends of the execution history of the systems.To increase predictability of COTS component we use cache Colouring, a technique widelyused to partition cache memory. Our main contribution is a WCET aware heuristic which par-tition task according to the needs of each task. Our experiments are made with CPLEX an ILPsolver with random tasks set generated running on preemptive system scheduled with earliestdeadline first(EDF).
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