An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things

03/11/2019
by   Utsav Banerjee, et al.
0

This paper presents a configurable lattice cryptography processor which enables quantum-resistant security protocols for IoT. Efficient sampling architectures, coupled with a low-power SHA-3 core, provide two orders of magnitude energy savings over software. A single-port RAM-based NTT architecture is proposed, which provides 124k-gate area savings. This is the first ASIC implementation which demonstrates multiple lattice-based protocols proposed for NIST post-quantum standardization.

READ FULL TEXT

Please sign up or login with your details

Forgot password? Click here to reset