Parity-check-aided Dynamic SCL-Flip Decoder with A Simplified Flip Metric for Polar Codes
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Since polar codes were proposed, improving the performance of polar codes at limited code lengths has received significant attention. One of the effective solutions is a series of list flip decoders proposed in recent years. To further enhance performance, we proposed a parity-check-aided dynamic successive cancellation list flip (PC-DSCLF) decoder in this paper. First, we designed a simplified flip metric, and proved by simulations that this simplification hardly affects the error-correction performance of list flip decoders. Subsequently, we optimized the existing allocation scheme for parity check (PC) bits, and then designed the first multi-PC-aided scheme with the dynamic characteristic for list flip decoders. The dynamic characteristic refers to an excellent ability to correct higher-order errors, which is beneficial for error-correction performance improvement. Meantime, the multi-PC-aided scheme to list flip decoders brings more flexible distributed check bits, which can narrow down the range for searching error bits and achieve a more efficient early termination. Simulation results showed that without error-correction performance loss, PC-DSCLF decoder shows up to 51.1 average complexity gain with respect to the state-of-the-art list flip decoder at practical code lengths. Lower average complexity leads to lower average energy consumption and lower average decoding delay.
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