Programmable Memristive Threshold Logic Gate Array

09/03/2018

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by   Olga Krestinskaya, et al.

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This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3× 4 TLG array is 1463 μ m^2 and 425 μ W, respectively.