Towards Accurate Performance Modeling of RISC-V Designs
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Microprocessor design, debug, and validation research and development are increasingly based on modeling and simulation at different abstraction layers. Microarchitecture-level simulators have become the most commonly used tools for performance evaluation, due to their high simulation throughput, compared to lower levels of abstraction, but usually come at the cost of loss of hardware accuracy. As a result, the implementation, speed, and accuracy of microarchitectural simulators are becoming more and more crucial for researchers and microprocessor architects. One of the most critical aspects of a microarchitectural simulator is its ability to accurately express design standards as various aspects of the microarchitecture change during design refinement. On the other hand, modern microprocessor models rely on dedicated hardware implementations, making the design space exploration a time-consuming process that can be performed using a variety of methods, ranging from high-level models to hardware prototyping. Therefore, the tradeoff between simulation speed and accuracy, can be significantly varied, and an application's performance measurements uncertain. In this paper, we present a microarchitecture-level simulation modeling study, which enables as accurate as possible performance modeling of a RISC-V out-of-order superscalar microprocessor core. By diligently adjusting several important microarchitectural parameters of the widely used gem5 simulator, we investigate the challenges of accurate performance modeling on microarchitecture-level simulation compared to accuracy and low simulation throughput of RTL simulation of the target design. Further, we demonstrate the main sources of errors that prevent high accuracy levels of the microarchitecture-level modeling.
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