High-level synthesis (HLS) is a process that automatically translates a
...
Formal verification of datapath circuits is challenging as they are subj...
Numerical hardware design requires aggressive optimization, where design...
Satisfiability Modulo Theory (SMT) solvers and equality saturation engin...
E-graphs are a data structure that compactly represents equivalent
expre...
Hardware implementations of complex functions regularly deploy piecewise...
Manual optimization of Register Transfer Level (RTL) datapath is commonp...
Recent e-graph applications have typically considered concrete semantics...
In machine learning, no data point stands alone. We believe that context...