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05/22/2023
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
Logic synthesis is the first and most vital step in chip design. This st...
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03/06/2023
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Oracle-less machine learning (ML) attacks have broken various logic lock...
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05/09/2022
Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution
Recent success in high-level synthesis ( HLS ) has enabled designing com...
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04/05/2022
Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis
Generating sub-optimal synthesis transformation sequences ("synthesis re...
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03/13/2022
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Post-Quantum Signature Schemes
NIST is standardizing Post Quantum Cryptography (PQC) algorithms that ar...
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11/01/2021
FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs
High-level synthesis (HLS) is the next emerging trend for designing comp...
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10/21/2021
OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis
Logic synthesis is a challenging and widely-researched combinatorial opt...
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10/11/2020
ASSURE: RTL Locking Against an Untrusted Foundry
Semiconductor design companies are integrating proprietary intellectual ...
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08/27/2020
Adversarially Robust Learning via Entropic Regularization
In this paper we propose a new family of algorithms for training adversa...
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07/26/2019