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06/29/2023
RowPress: Amplifying Read Disturbance in Modern DRAM Chips
Memory isolation is critical for system reliability, security, and safet...
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05/12/2023
Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses
The performance and capacity of solid-state drives (SSDs) are continuous...
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04/03/2023
TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems
Processing-in-memory (PIM) promises to alleviate the data movement bottl...
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12/13/2022
ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems
Partitioning applications between NDP and host CPU cores causes inter-se...
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12/09/2022
TargetCall: Eliminating the Wasted Computation in Basecalling via Pre-Basecalling Filtering
Basecalling is an essential step in nanopore sequencing analysis where t...
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10/16/2022
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory
Recent nano-technological advances enable the Monolithic 3D (M3D) integr...
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09/18/2022
GenPIP: In-Memory Acceleration of Genome Analysis via Tight Integration of Basecalling and Read Mapping
Nanopore sequencing is a widely-used high-throughput genome sequencing t...
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09/12/2022
Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory
Bulk bitwise operations, i.e., bitwise operations on large bit vectors, ...
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09/01/2022
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
Long-latency load requests continue to limit the performance of high-per...
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06/10/2021
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
DRAM is the dominant main memory technology used in modern computing sys...
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05/08/2021
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
Data movement between the CPU and main memory is a first-order obstacle ...
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04/15/2021
pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation
Data movement between main memory and the processor is a significant con...
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10/19/2020
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
Graphics Processing Units (GPUs) employ large register files to accommod...
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09/17/2020
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
DRAM Main memory is a performance bottleneck for many applications due t...
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04/21/2020
NOM: Network-On-Memory for Inter-Bank Data Transfer in Highly-Banked Memories
Data copy is a widely-used memory operation in many programs and operati...
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02/19/2019
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices
Low-cost devices are now commonplace and can be found in diverse environ...
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12/30/2018
ORIGAMI: A Heterogeneous Split Architecture for In-Memory Acceleration of Learning
Memory bandwidth bottleneck is a major challenges in processing machine ...
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10/22/2018